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INTEGRATEDCIRCUITS
DATASHEET
SAA7145 PCIMultimediaBridge
ProductSpecifications
November30th,1995
Philips Semiconductors
ThisdatasheetwasmanuallyretypedonSeptember2004byLucaBonissi.Itcouldcontainsometypos.PhilipsSemiconductorsisnotresponsible aboutanywronginformationderivatefromthesetypos.
PhilipsSemiconductors PCIMultimediaBridge
Pantera
DataSheet SAA7145
Legalstuff: Thisdocumentcontainspreliminaryinformationandisintendedforinternaluseonly.Datasubject tochangewithoutnotice.
PhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationreservetherighttomakechanges,without notice,intheproductdescribehereininordertoimprovedesignand/orperformance.PhilipsSemiconductorsassumes noresponsibilityorliabilityfortheuseofthisproduct,conveysnolicenseortitleunderanypatent,copyright,ormask workrighttotheseproducts,andmakesnorepresentationorwarrantiesthattheseproductsarefreefrompatent, copyright,ormaskworkrightinfringementunlessotherwisespecified.Applicationthataredescribedhereinarefor illustrativepurposesonly.PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbe suitableforthespecifiedusewithoutfurthertestingormodification. LIFESUPPORTAPPLICATIONS PhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationproductsarenotdesignedforuseinlife supportappliances,devices,orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorth AmericaCorporationProductcanreasonablybeexpectedtoresultinapersonalinjury.SemiconductorsandPhilis ElectronicsNorthAmericaCorporationcustomersusingorsellingSemiconductorsandPhilipsElectronicsNorth AmericaCorporationProductsforuseinsuchapplicationsdosoattheirownriskandagreetofullyindemnity SemiconductorsandPhilipsElectronicsNorthAmericaCorporationforanydamagesresultingfromsuchimproperuse orsale. SemiconductorsandPhilipsElectronicsNorthAmericaCorporationregistereligiblecircuitsundertheSemiconductors ChipProtectionAct. (c)PhilipsSemiconductors,1995
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TableofContents
1.Features.......................................................................................................................................................................4 2.GeneralDescription.....................................................................................................................................................5 3.ImplementationExamples............................................................................................................................................7 4.SAA7145RegisterSet.................................................................................................................................................8 5.VideoPort..................................................................................................................................................................10 5.1.VideoPortControl..............................................................................................................................................10 5.2.CCIR656Mode.................................................................................................................................................12 5.3.DMSD2Mode.....................................................................................................................................................13 6.Scaler.........................................................................................................................................................................14 6.1.ActiveWindowSelection....................................................................................................................................14 6.2.Scaling...............................................................................................................................................................15 6.3.Filtering..............................................................................................................................................................16 7.PixelFormatter...........................................................................................................................................................17 8.VideoDMAControl.....................................................................................................................................................18 8.1.NonInterlacedVideoOutput..............................................................................................................................20 8.2.InterlacedVideoOutput......................................................................................................................................20 9.AudioInputPort.........................................................................................................................................................21 10.DEBIPort.................................................................................................................................................................23 10.1.DEBITiming.....................................................................................................................................................25 11.I2CPort....................................................................................................................................................................28 12.RegisterProgrammingSequencer(RPS).................................................................................................................30 12.1.RPSControl.....................................................................................................................................................30 12.2.CommandSet..................................................................................................................................................31 12.2.1.LDREG......................................................................................................................................................31 12.2.2.STREG......................................................................................................................................................32 12.2.3.STOP........................................................................................................................................................32 12.2.4.JUMP........................................................................................................................................................32 12.2.5.IRQ................................................................................................... .........................................................32 12.2.6.NOP..........................................................................................................................................................33 12.2.7.WAIT.........................................................................................................................................................33 12.2.8.CHECK.....................................................................................................................................................33 12.2.9.PAUSE......................................................................................................................................................33 12.2.10.SET.........................................................................................................................................................33 12.2.11.CLR.........................................................................................................................................................33 12.3.RPSFlags........................................................................................................................................................34 13.Clipper......................................................................................................................................................................35 14.PCIInterface............................................................................................................................................................37 14.1.ThePCIMaster................................................................................................................................................38 15.TheEventManager..................................................................................................................................................39 15.1.InterruptControl...............................................................................................................................................39 15.2.EventMonitors.................................................................................................................................................40 16.GeneralPurposeI/OPort(GPIO).............................................................................................................................42 17.PinList.....................................................................................................................................................................43 18.PinOut.....................................................................................................................................................................44 A.AppendixA:RPSProgrammer'sReference...............................................................................................................45 A.1.ProgrammingExamples......................................................................................................................................45 A.2.RPSBasics.........................................................................................................................................................45 A.3.UsingRPStosendvideototwolocations...........................................................................................................46 B.AppendixB:InterfacingtoStandardPhilipsParts.......................................................................................................48 B.1.ProgrammingHints.............................................................................................................................................48 C.AppendixC:PackageOutline.....................................................................................................................................50 November30th,1995 3 Revision1.3.1
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1.Features
* * * * * * * * * * * * * * * * * *
Fullsize,fullspeedvideodeliverytoframebufferorsystemmemory FullBandwidthPCIbusMaster(upto132MB/sec) D1(CCIR656)VideoInputPort DMSD2compatible 128DwordVideoFIFO SimpleArbitrarySizeScaling HorizontalFiltering ColorSpaceConversion Supportforallstandardpackedpixelformats SupportforPixelDithering VideoMaskClipping Videosynchronizedprogrammingcontrol(RPS) AudioCaptureviaI2Sinputport I2CBusport DEBI(DataExpansionBusInterface)portforusewithexternaldevices FIFOOverflowDetectionand"graceful"recovery Supportforeventanalysis 160pinpackage
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2.GeneralDescription TheSAA7145isaMultimediaPCIbridge.TheSAA7145canbeusedtoplacearealtimevideo anywhereinsystemorvideomemory.Itsupportsmanydifferentoutputformatsforextended compatibilitywithanyframebuffer.Thevideoimagecanbescaledtoanarbitrarysizebythe internalscalingunit.Thevideocanalsobecroppedtoanarbitraryshapetosupportvideowindow occlusionsandgraphicsoverlay. TheSAA7145alsohassupportforaudiocapture.AudiocaptureisaccomplishedthoughaI2S interface.TheaudioporticonfigurabletoworkwitharangeofaudioAtoDconverters. Ingeneralitoffershigherperformancethanit'spredecessortheSAA7116andaddsseveralnew features.
Function videotoPCI PCItovideo PackedOutputModes RGB32 RGB24wrapped RGB16 RGB15 Dithering PlanarOutputModes VideoFlip D1VideoPort DMSD2Compatible 24bitVideoPort ArbitraryVideoScaling VerticalFiltering HorizontalFiltering Zoomup BCSControl I2CPort DEBIPort AudioInputPort AudioOutputPort GPIOPorts RectangularClipping MaskClipping ChromaKeyClipping RPSControl GammaCorrection ColorSpaceConverter PCIRetryCapable PackageSize 7116 7145 7146 2 2 2 4 206

4 160
160
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BelowisadiagramshowingthemajorblocksoftheSAA7145.
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3.ImplementationExamples BelowisthesimplestuseoftheSAA7145.Averylowcostvideoinputcardcanbeachievedin thisway.Onlytwomajorcomponentsarerequired:SAA7145VPCIandtheSAA7110OFC1or SAA7111VIP.
BelowinanotheruseoftheSAA7145.AlowcostMPEGplaybackcardcanbeachievedwitha smallamountofgluelogic.
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4.SAA7145RegisterSet AtableoftheinternalregistersoftheSAA7145isprovidedbelow.Theseregistersareaccessed byaddingtheoffsettothevaluecontainedinthePCIConfigurationBaseAddressRegister. AccessestotheRegisterspacearepermittedbyDwordsonly.ByteandWordaccesseswillnot causeanerrorbywillnotcorrectlyprogramtheregister.
OFFSET 00 04 08
0C 10
14
18
1C
20 24
28
NAME VDBA VDPA VDPEN VDMAC EVID VBS VTHR VEND PFMT VFLIP VPCH VPCTL XWC XWS XWZ YWC YWS YWZ FSCTL ILO FMODE XSCI YSCI YPR YPO YPE CDBA CDF CPO CPIX CLINE CDMAC ECLIP CEND CPOL CPCH
Shadowed yes yes yes
BITS 31:0 23:2 0 31 27:25 23:21 20:19 18:16 15 12:0 15:0 25:16 9:0
yes yes
yes 25:16 9:0 yes 31 30:28 26:16 10:0 yes 25:16 9:0 31:2 28:24 21:16 9:0 yes 31 20:19 16 9:0
yes yes
DESCRIPTION VideoDMABaseAddress VideoDMAProtectionAddress EnableVideoDMAProtection VideoDMAControlRegister EnableVideo VideoDataBurstTransferSize VideoFIFOThreshold EndiannessControls OutputFormat(rgb32,etc.) VerticalFlip LinePitch VideoPortControl HorizontalWindowControlRegister HorizontalWindowStart HorizontalWindowSize VerticalWindowControlRegister VerticalWindowStart VerticalWindowSize FilterandScalerControlRegister InterlaceOutput HorizontalFilterMode HorizontalScalingIncrement VerticalScalingIncrement VerticalPhaseRegister VerticalPhaseOffsetOdd VerticalPhaseOffsetEven ClipMaskDMABaseAddress ClipDataFormatRegister PixelOffsetintoDword NumberofDwordsperLineofClipMask NumberofLinesofClipMask ClipperDMAControlRegister EnableClipper EndiannessControl ClipperPolarity LinePitch 8 Revision1.3.1
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PhilipsSemiconductors PCIMultimediaBridge OFFSET 2C NAME LCR SLCT TLCT ADBA ADPA ADMAC EAUD AEND AFMT ARNG RPSPTR ERPS RPSR RPSP ERPSP RPSTO TOSEL TOV TOP ISR IER IMR ECR ECT ECC GPIOC DEBICFG DEBIDAT DEBICMD IICTRF IICB2 IICB1 IICB0 IICCTL IICSC IICCC IICSTA UTIL rsvd Shadowed yes BITS 25:16 9:0 31:2 16:2 31 19 17:16 3:0 31:2 0 31:11 0 no 29:28 27:24 23:0 31:0 31:0 31:0 19:0 19:0 15:0 31:0 31:0 31:0 31:0 31:24 23:16 15:8 7:0 no 10:8 7:0 31:0 31:0
Pantera DESCRIPTION LineCounterRegister Sourcelinecounterthreshold Targetlinecounterthreshold AudioDMABaseAddressRegister AudioDMAProtectionAddress AudioDMAControlRegister EnableAudioDMA AudioDataEndianness AudioFormatControl DMAInterruptRange RPSPointerAddress EnableRPSbit RPSPageRegister RPSPageAddress RPSPageErrorEnable RPSTimeOut RPSTimeOutSelector RPSVideoTimeOutValue RPSPCITimeOutValue InterruptStatus InterruptEnable InterruptMonitor EventCounterRegister EventCounterThreshold EventCounterControl GPIOControl DEBIConfigurationRegister DEBIDataRegister DEBICommandRegister I2CTransferControlRegister I2CDataByte2 I2CDataByte1 I2CDataByte0 I2CTransferControl I2CStatusandClockRegister I2CClockControl I2CStatus UtilityRegister Reservedforfutureuse
DataSheet SAA7145
30 34 38
no no no
3C 40
no no
44
48 4C 50 54 58 5C 60 64 68 6C 70
no no no no no no no no no no no
74
78 7C
no no
Moredetailedregisterdescriptioncanbefoundintheassociatedsection.
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5.VideoPort ThevideoportoftheSAA7145isaYUV4:2:2inputonlyport.Itcanbeconfiguredtoaccept8bit timemultiplexedYUVdatainaccordancewithCCIR656ortheportcanalsobeconfiguredasa 16bitportforbackwardcompatibilitywithOCF1andDMSD2.Apixelclockinputandapixel qualifierareusedtoclockinthevideosamples.Theportcircuitrycandetectorcreateafield sequenceifneededoffieldinformationcanbebroughtinontheFIDpin.IftheFIDpinisuseda highvalueindicatesanoddfield,lowindicateseven. 5.1.VideoPortControl TheVideoportoftheSAA7145iscontrolledbytheVideoPortControl(VPCTL)register.This registerconfiguresthevideoporttomatchtheincomingstreamandconfiguressyncandfield detection. TheVideoPortSize(VPZ)bitselectsbetweenan8or16bitport. TheExternalSyncSource(XSS)bitselectsbetweenencodedsyncsignalsorsyncbroughtinthe pins.8bitmodeonly. SyncOutputEnable(SOE)enablesthedecodedsyncsignalstobeplacedontheHSandVS pins.8bitmodeonly. TheFieldDetectbits(FD[1:0])areusedtoselecthowfieldchangesaredetected.Modesare Normal(00),NoiseLimit(01),ForceToggle(10)andExternal(11).InNormalandNoiseLimited modestheReferenceEdgeofVerticalsync(definedbelow)isusedtodetectthefieldID.IfH Syncishighwhenthereferenceedgeoccursthatfieldisdetectedaseven,iflowthefieldisodd. ForceOdd(FODD)forcesallfieldstobehandledasoddfields.SwapFields(SF)invertsthefield bit.IfFODDisactivethenallfieldsareeven. ReferenceEdgeforVerticalSync(REVS):thisbitisusedtoselectthepolarityofthetrailingedge ofverticalsync.Thisedgeisalsousedtostartthesourcelinecounter.Aoneinthisbitresetsthe sourcelinecounterontherisingedgeofverticalsync,azeroresetsthecounteronthefalling edge.Thisbitalsodefinestheedgeofverticalsynconwhichfieldsaredetected. ReferenceEdgeforHorizontalSync(REHS):thisbitisusedtoselectthepolarityoftheleading edgeofhorizontalsync.Thisedgeisalsousedtostartthesourcepixelcounter.Aoneinthisbit resets,thesourcepixelcounterontherisingedgeofhorizontalsync,azeroresetsthecounteron thefallingedge. EVEND:settingthisbitdisablesthedisplayofevenfields. ODDD:settingthisbitdisablesthedisplayofoddfields. TWOS:UandVcomponentsinTwoscomplement.IfthisbitissetthentheUandVcomponents oftheinputstreamareintwoscomplementformatratherthanunitary. TEST:thisbitisusedonlyintesting.Thisbitmustbezerofornormaloperation.
VPCTL Bits Name
Offset:0C Description
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PhilipsSemiconductors PCIMultimediaBridge VPCTL 15 14:12 11 10 9 8 7 6 5 4:3 TEST rsvd EVEND ODDD REVS REHS TWOS SF FODD FD[1:0] Offset:0C 1=EnterTestmode 0=NormalOperation Reserved Turnoffevenfields Turnoffoddfields
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DataSheet SAA7145
ReferenceEdgeforVerticalSync ReferenceEdgeforHorizontalSync UandVComponentsinTwo'sComplement SwapFields(1enables) ForceOdd(1enables) FieldDetectMode 00=Normal 01=NoiseLimited 10=ForceToggle 11=ExternalInput(FID) SyncOutputEnable 1=EncodedSyncplacedonpins ExternalSyncSource 1=Synccomesinonpins 0=Syncisencodedinstream VideoPortSize 1=16bitport 0=8bitport
2 1
SOE XSS
0
VPZ
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5.2.CCIR656Mode InCCIR656mode(alsocalledD1video),syncsignalscanbeencodedinthestreamorbrought inonseparatesyncinputs.Thesyncpinscanbealsousedasoutputswhenexternal synchronizationtotheinputsourceisrequired.Thepixelrateisequaltoonehalftheclockrate withaluminancesamplearrivingeveryotherclock.Chrominancesamplesarriveonthe1stand3rd clocksinthepatternUYVY.PixeldatamaybequalifiedbytheuserofPXQ. InthismodevideodatacomesinonVPI[15..8]pins.VPI[7..0]areignored.
clockedge n n+1 n+2 n+3 sample 1 1 2 2 VPI[15:8] U Y V Y
Inthismodeverticalandhorizontalsynchronizationsignalscanbeencodedintothevideostream. TheSAA7145iscapableofdecodingthesecodes.EachcodeisprecededbytheprefixFF,00,00 thenext8bitscontaintheencodedfieldnumber,verticalandhorizontalinformationand4bit paritynibble.TheSAA7145doesnotdoparitycheckingorerrorcorrectionofencodeddata.
BitNo. 7 1 6 F 5 V 4 H 3 P3 2 P2 1 P1 0 P0
F=Fieldbit. 0foroddfields 1forevenfields. V=VBIbit. 1duringVerticalBlanking 0elsewhere H=HBIbit. 0indicatesStartofActiveVideo(SAV) 1indicatesEndofActiveVideo(EAV) ThismodeiscompatiblewiththeSAA7111andotherdevices.
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5.3.DMSD2Mode TheDMSD2formathasluminance(Y)dataonone8bitportandchrominance(U&V)datatime multiplexedonasecond8bitport.Theclockrunsattwicepixelrateinthismodewithaclock qualifieronPXQatonehalftheclockrate.Syncsignalsarealwaysbroughtinonthesyncinput pins. InthismodevideodataarrivesinbytepairsofYUandYVwithYdataappearingonVPI[15..8] andtheUVdataappearingonVPI[7..0].UsamplesareoddandVsamplesareeven.
clockedge n n+1 n+2 n+3
sample 1 1 2 2
VPI[15:8] Y Y Y Y
VPI[7..0] U V U V
ThismodeiscompatiblewiththeSAA7110,SAA7191andother16bitdevices.
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6.Scaler TheScalerandHorizontalFilterareinthesamephysicalblock. Horizontalscalingisaccomplishedbyacombinationofpixeldroppingandaveraging.Vertical scalingisdonebylinedropping.Forinterlacedvideo,linedroppingcanbedonesinglyorby droppinglinepairs.AwindowisselectedfromtheincomingvideostreamandiscalledtheActive VideoWindow.Onlythepartofvideolocatedinsidethewindowisscaled,therestisignored. 6.1.ActiveWindowSelection Selectionoftheactivewindowofthevideostreamisaccomplishedbyasetoffourregisters.Only thedatawithintheactivewindowispassedalongtothescalingunit,allothervideodatais discarded.TheverticalwindowischosenusingtheYWindowsStart(YWS)andYWindowSize (YWZ)registers.TheYWSregisterisloadedwiththelinenumberofthefirstlineofactivevideo. TheYWXregisterisloadedwiththetotalnumberoflinestobepassedontothescaler.A horizontalwindowwithinalineischosenfromtheinputstreambytwosimilarregisters,XWindow Start(XWS)andXWindowSize(XWZ). YWindowStart(YWS):countthisnumberoflinesfromtheReferenceEdgeofverticalsyncbefore startingthecapture.Example:iftheregistercontainsavalueof20thethe20thlineafterthe referenceedgewillbethefirstonesenttothescaler.Thisregisterisusedasanoffsettothestart ofactivevideofromthesyncedgeprogrammedintheVPCTL.YWShasarangeof1to1024,but mustbeprogrammedwithavaluelessthanthetotalnumberoflinesinonefieldofvideo. YWindowSize(YWZ):thisisthenumberoflinestobesenttothescaler.Usuallythisis programmedwiththenumberoflinesofactivevideo.YWZhasarangeof1to1024.TheY windowsizecanbeprogrammedwithamaximumvalueofthetotalnumberoflinesinafield (includingblanking)minustwo. XWindowStart(XWS):countthisnumberofpixelsfromtheReferenceEdgeofhorizontalsync beforestartingthecapture.Example:iftheregistercontainsavalueof40thenthe40thpixelafter thereferenceedgewillbethefirstonesenttothescaler.Thisregisterisusedasanoffsettothe startofactivevideofromthesyncedgeprogrammedintheVPCTL.XWShasarangeof1to 1024,butmustbeprogrammedwithavaluelessthanthetotalnumberofpixelsinoneline. XWindowSize(XWZ):thisisthenumberofpixelstosendtothescaler.Usuallythisis programmedwiththenumberofpixelsisalineofvideo.XWZhasarangeof1to1024.TheX windowsizecanbeprogrammedwithamaximumvalueofthetotalnumberofpixelsinaline (includingblanking)minus8.
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TheabovediagramshowsthetypicaluseofActiveWindowRegisters.Itispossiblehoweverto capturesmallerorlargerwindowsorevenmorethanone.Inthecasewheremorethanone windowiscapturedthesecondwindow'sYWSisstillmeasuredfromtheVerticalSyncedge,not thepreviouswindow. 6.2.Scaling Scalingiddonebylineandpixeldropping.Boththehorizontalandverticalscalingandfilter modesaresetbyprogrammableregisters. Videoscalingiscontrolledbyfourregisters:YScalingIncrement(YSCI),YScalingOffset(YPO), YScalingOffset(YPE)andXScalingIncrement(XSCI). Thevaluesforeachofthereregistersisdeterminedbyformulasshownbelow. SY=#outputlines/#inputlines ThenumberofinputlinesisprogrammedinYWZ. YSCI=INT(1024xSY) Ininterlacemode,forsinglelinescaling: YPO>YPE Recommend: YPO=768,YPE=256forSY=1to2/3and1/3to0 YPO=683,YPE=341forSY=2/3to1/3 Ininterlacemode,forlinepairscaling YPO=YPE=512 Innoninterlacemode, YPO=YPE=512
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SX=#outputpixels/#inputpixels(perline) ThenumberofinputpixelsisprogrammedinXWZ. XSCI=INT(1024xSX)
FSCTL Bits 31 30:28 26:16 10:0 Name ILO FMODE XSCI YSCI Offset:18 Description InterlaceOutput HorizontalFilterMode HorizontalScalingIncrement VerticalScalingIncrement
6.3.Filtering TheHorizontalfiltermustbeprogrammedtomatchthescalingfactorchosen.Lowerfiltermodes canbeusedbutforbestresultusetheformulabelow.Usingtoohighofafilterfactorwillyield unpredictableresults. FilterMode(FMODE):thisregistercontrolthefilteringfunctionoftheSAA7145.TheFMODE valueisprogrammedintheFSCTLregister.Iffilteringistobeusedthefollowingformulashould beusedtocalculatethepropervalueforFMODE.IffilteringisbypassedFMODEshouldbe loadedwithzero(orone). FMODE=TRUNC(LOG2(1/SX))+1
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7.PixelFormatter ThePixelformatterisresponsibleforputtingthepixelinformationinthecorrectbytelanesand sizingittotheproperoutputformat.ItismanagerbytheVideoDMAcontrollertoensurethatthe dataisproperlyalignedwiththemaskinginformationreceivedfromtheClipper.Thepixel formatterorganizestheinformationfromthescalerbasedonbitdepth,colorspaceandwhether thetargetwantsbigorlittleendianformat.ThePFMTvalueisprogrammedintheVDMAC register. TheColorSpaceConverterisselectedautomaticallybythemodeswhichrequireit. Thepixelformattersupportsthefollowingmodes:
PFMT 0 1 2 3 4 5 6 7 RGB32(aRGB) RGB24(RGBR...) RGB16(5:6:5) RGB15(a:5:5:5) YUV16(CCIR) Grayscale(YYYY) RGB16dither RGB15dither
Mode
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8.VideoDMAControl TheVideoDMAcontrolleroftheSAA7145issimilartotheSAA7116withseveralenhancements. TheSAA7145iscapableofmultipletransfersperbusrequest.Theburstsizeisprogrammable from1to65inpowersoftwoplusasettingforunlimitedlength.SincetheSAA7145alsohas multiplemastersaninternalarbiterhelpstoscheduleefficientbususe.TheSAA71445isalso capableofacceptingandproperlyhandlingPCIcyclesterminatedwithaRetry. TheSAA7145alsocontainslogicfor"gracefully"handlingFIFOoverflowandaddressprotection violations.AFIFOoverflowisusuallycausedbyamomentaryincreaseinbususage.The SAA7145recoversfromanoverflowassoonasspaceisavailableintheFIFO.Aprotection violationisusuallycausedbyalossofsignalintegrityofimproperprogramming.TheSAA7145 allowsvideotocontinuerunningfromthenextverticalsyncaftertheviolation.Eachofthese conditionscangenerateaninterrupt,ifenabled. DMABaseAddress(VDBA):thebyteaddressofthefirstpixeltobedisplayed.Thisistheupper leftcornerofthevideopicture.Theuppereightbitsoftheaddressarefixed,onlythebottom24 bitsareincrementedduringDMA.Thishastheeffectoflockingvideointoone16megabyte space. ProtectionAddress(VPA):Thisvalueisusedasasafetyvalveforaddressoverruns.Intheevent thattheDMAmastertriestooverwritetheendofthetargetbuffer.Thisprotectionensuresthatthe programdataareasandsystemcontrolregistersarenotinadvertentlywrittento.Thisfeatureis enabledbywritingaonetobitzero(VDPEN).InnormaloperationtheProtectionaddresschecks toseeifthetargetaddressisabovethreshold.IftheVFLIPbitisset(seebelow)theProtection addresscheckstoseeifthetargetaddressisbelowthreshold. TheVideoDMAControlRegister(VDMAC)containsmanycontrolsforvideoDMA.Theyare outlinedbelow.
VDMAC Bits 31 28:25 23:21 20:19 18:16 15 12:0 Name EVID VBS VTHR VEND PFMT VFLIP VPCH Offset:08 Description EnableVideoCapture VideoDataBurstTransferSize VideoFIFOThreshold EndiannessControls OutputFormat VerticalFlip VideoLinePitch
EnableVideo(EVID):enablesvideodatatobeplacedinthevideoFIFOandenabledDMA transfers. BurstSize(VBS):anumberprogrammingthesizeofthetransferinthepowerof2.Afterthisthe DMAyieldsownershipofthebustothenextinternaldevice.Programminga7inthislocation enablesunlimitedlengthtransfers,atleastuntilthelatencyTimerrunsout.Thisisnot recommendedwhenotherfunctionsareinuse.
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PhilipsSemiconductors PCIMultimediaBridge Value 0 1 2 3 4 5 6 7 BurstSize 1 2 4 8 16 32 64 unlimited
Pantera
DataSheet SAA7145
FIFOThreshold(VTHR):ThisvaluedetermineshowmanyDwordstostoreintheFIFObefore tryingtoacquirethebus.Thisregisterwithmultiplesof16Dwordsasshownbelow.Regardlessof theamountofdataintheFIFOthedataisalwaysflushedattheendofthehorizontalwindow.
Value 0 1 2 3 4 5 6 7 FIFOThreshold 1 16 32 48 64 80 96 112
Endianness(VEND):Thesetwobitsselectwhetherbigorlittleendianaddressingisused.Also provides2byteswap.
Value 00 01 10 11 Swapping none 2byte(1234=>3412) 4byte(1234=>4321) reserved
VerticalFlip(VFLIP):ifthisbitissetthenumberprogrammedinVPCHisintwo'scomplement formattoindicateavertical(topdown)flip.Clippinginnotavailableinthismode. VideoPitch(VPCH):Pitchisdefinedasthedifferenceinaddressbetweentwoverticallyadjacent pixels.Thisnumbercanbeprogrammedintwo'scomplementformattoindicateavertical(top down)flipiftheVPCHbitisset.
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8.1.NonInterlacedVideoOutput TodisplaynoninterlacedvideotheSAA7145startsateachverticalsyncbyloadingtheVideo DestinationPointer(VDP)withthecontentsofVideoDMABaseAddressRegister(VDBA).When thestartoftheactivewindowisreachedtheSAA7145beginsbusmasterwritestothetarget.At theendofeachlinethePitchregisterisaddedtotheVDPandtheSAA7145isthenreadyto precessthenextline.ThiscontinuesuntiltheendoftheActiveVideoWindow. TheVDBAisloadedwiththeaddressofthetopleftpixeltobedisplayed.TheProtectionAddress isloadedwiththeaddressofthebottomleftpixeltobedisplayedplus1linepitchplus1Dword. 8.2.InterlacedVideoOutput Therearesomespecialconsiderationstobemadewhendisplayinginterlacedvideo.Toenable interlacingtheILObitmustbesetto1.Thishasseveraleffects.OnevenfieldsthePitchis automaticallyaddedonetotheVideoDMABaseAddressafterithasbeenloadedintotheVideo DestinationPointer.Normalfullsizeinterlacerequiresthepitchtobeaddedtwicebetweeneach line,thisoccursautomaticallywhenILOisset. Astheimageisscaleddownandsomelinesareremoved,thescalerandtheDMAcontrollerwork togethertomakesureeachlineofvideoisproperlyinterlaced.Scalingcanbebylinepairs (YPO=YPE)orbysinglelines(YPO>YPE). Thearrangementofclipdatainmemoryremainsthesameasifalargernoninterlacedimage weredisplayed.TheSAA7145takescaretousetheproperlineofclipdata. TheVDBAisloadedwiththeaddressofthetopleftpixeltobedisplayed.TheProtectionAddress isloadedwiththeaddressofthebottomleftpixeltobedisplayedplus2linepitchedplus1Dword.
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9.AudioInputPort TheaudioinputportoftheSAA7145isastereoI2Sport. TheAudioDMAcontrolleroperatesmuchlikethevideoDMA.TheAudioBaseAddressRegister (ADBA)pointstothefirstlocationinmemorywheredataistobestored.TheProtectionAddress (ADPA)isusedasadatawrappingpoint,whentheDMApointerreachesthisaddressit reinitializesitselfwiththeBaseAddressandimmediatelycontinues.Sinceaudioiscontiguous data,theDMAfillsthismemoryrepeatedlyinacircularfashion.TheADPAinonlywritableinthe bottom16bits,theupperbitsaretakenfromADBA.Thislimitsthesizeoftheaudiomemory buffertoamaximumof64Kbytes. Largerbufferscanbeemulatedbysplittingthebufferintosmallerpartsandcollectingthedatain onepartwhiletheDMAiswritingtotheother.Toensurethattheaudiodataiscollectedproperly bytheHost,aninterruptcanbegeneratedastheDMApointercrossesthresholdsdeterminedby theARNGregister.Thesethresholdsarerelatedtothetargetaddressboundaries.Avalueof000 setstheinterruptwheneverthebottom8bitsofthetargetaddressarezeroesorevery256bytes. 001setstheinterruptwhenthebottom9bitsarezeroesonupuntilthevalueof111for15zeros orevery32K. TheI2Sinterfaceisatimingslave.Itreceivestheaudiodataandparallelizesitinto16or8bit words.ThesewordsareplacedintheaudioFIFO.TheaudioFIFOisonly8Dwordsdeep,butis stillbigenoughtostore2videolinesofstereo16bitaudiodataat44.1Khz.TheFIFOunloader alwaysattemptsburstsof4DwordsofdataacrossthePCIbustothetargetlocation.Withsucha lowdataratetheprobabilityofaFIFOoverflowisremote,butifitdoesoccurtheAudioFIFO Overflow(AFO)interruptbitisset. Acquisitionalwaysbeginswiththeleftchannel,indicatedbyWSbeinglow.
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ADBA Bits 31:2 ADPA Bits 16:2 ADMAC Bits 31 19 Name EAUD AEND Name ADPA Name ADBA
Offset:30 Description AudioDMABaseaddress Offset:34 Description AudioDMAProtectionaddress Offset:38 Description EnableAudioDMA Endianswappingcontrol 0=noswapping 1=fourbyteswap(4321=>1234) AudioFormatControl 00=16bit,risingedge 01=8bit,risingedge 10=16bit,fallingedge 11=8bit,fallingedge DMAInterruptRange
17:16
AFMT
2:0
ARNG
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10.DEBIPort DEBI(DataExpansionBusInterface)isasixteenbitauxiliarydataportwhichcanbeusedto controlanexternalparalleldevice.LargeamountsofdatacanbetransferredusingthedataFIFO. ItisthisportthatenablestheSAA7145tosupportMPEGdecodersandotherparallelaccessICs. TheDEBIportcanbeaccesseddirectlyorviaRPS. TheDEBIportisa16bitmultiplexedaddressanddatabuswithcontrolsignals.Thefivecontrol signalscanbeconfiguredtooperateasIntelorMotorolastyleofsignaling.Asixthpinisusedto transmitaninterruptrequesttothePCIbus.Thisinterruptismaskable. TheDEBIportiscontrolledbytheuseofthreeregisters.Theconfigurationregister(DEBICFG) containsinformationregardingthetransfermodeofoperation(Intel/Motorola,Big/LittleEndian, etc.).TheCommandRegister(DEBICMD)containsthetargetaddressandtransferdirectionand thelengthofthedataphase.ThetransferisinitiatedbythewritetotheDEBICMDregistersoit mustbethelastregisterprogrammed.Ifthedataphaseid4bytesorlessthenthedataisplaced intheDataRegister(DEBIDAT).Ifthetransferismorethan4bytesthentheaddressinsystem memoryofthefirstlongwordofdataisplacedintheDEBIDATregister.Ifthedataphaseisless thanfourbytestherelevantdatashouldalwaysbeplacedintheLSbyteD[7:0]. 16bitaccessestounalignedslaveaddressesareautomaticallysteppeddownto8bittransfers. LongburstsofdataaretransportedtoorfromtheDEBIportbyusingtheDEBIdataFIFO.This FIFOisusedasaflowcontrolforDEBIdatasincetheprocesswillmostlikelybeasynchronousto RPSandPCI.TheDEBIdataFIFOisbidirectionalandis32Dwordsdeep. TheSmartSlave/DumpSlaveoptionallowstransferstodeviceswhichdonotrespondwith RDY/DTACK.Adumpslavetransferisterminatedbythetimeoutvalueonly.OndumpIntelstyle readsthedataissampledattherisingedgeofRDN.OndumpMotorolastylereadsthedatais sampledattherisingedgeofxDS. XIRQcanbeusedtoregulatetheflowofdatato/fromtheDEBIportiftheXIRW_WAITflagisset. Ifset,assertionofXIRQwillcausetheDEBIporttostallafterthecurrenttransaction.Execution willcontinueifXIRQisdeasserted,orthehostcanusethistimetoreprogramtheDEBIslave device.TheactivelevelofXIRQisprogrammableviatheXIRQPOLpin. IfINCRisenabledtheaddresspresentedtotheslaveisincrementedbetweeneachdataphase.If itisdisabledthesameaddressisusedrepeatedly.Thelattermodeisusefulforaccessing externalFIFOs. IsSLAVE16isenabledthe7145presents16bitsofdataperdataphase.Ifdisabledthe7145will presentthedata8bitsperdataphase.DataispresentedonlyonXAD[7:0]inthismode. DataBandwidthislargelydependentonslavespeed.Howeverifthetargetacknowledges immediatelythecycletimesare7PCIclocksperslavewrite(PCIread)and10PCIclocksfor slavereads(PCIwrite).Fromthisitcanbedeterminedthatthemaximumslavewritebandwidthis about9.4MB/sandforreadsisabout6.6MB/sfora16bitslave.8bitperformanceisexactlyhalf ofthe16bitvalues.
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DEBICFG Bits 29 28 Name XIRQPOL SS/DS
Offset:64 Description ThisbitrepresentstheactivelevelofXIRQ SmartSlave/DumpSlave 1=Smart 0=Dump Ifenable,XIRQcausestheDEBIporttoholdoffpendingaccessesuntilcleared Reserved TerminatethetransferafterthismanyPCIclocks Endianswappingcontrol 00=noswapping 01=twobyteswap(4321=>2143) 10=fourbyteswap(4321=>1234) 11=reserved Indicatedtheslaveisabletoserver16bittransfer Enablesaddressincrementforblocktransfer Intelstylebusifhigh,Motorolastyleislow TimerEnable,1enables Offset:68 Name DEBIDAT Description DataorAddressofData Offset:6C Name BLOCKLEN WRITE_N Description DataBlockLengthinBytes TransferDirection 1=Read 0=Write SlaveTargetAddress
27 26 25:22 21:20
XIRQ_WAIT rsvd TIMEOUT SWAP
19 18 17 16 DEBIDAT Bits 31:0 DEBICMD Bits 31:17 16
SLAVE16 INCR IN/MO TIEN
15:0
A16_IN
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10.1.DEBITiming OnthefollowingpagesaretimingdiagramsoutliningthebasicfunctionalityoftheDEBIportin boththeIntelandMotorolastylesignalingprotocols.Belowarethetimingtables.
Parameter tas tah tdsr tdhr tdsw tdhw tdz tacc tdtack min. 20 20 20 5 20 0 0 0 Tc max. Tc Tc Tc Tc 4xTc * ** units ns ns ns ns ns ns ns ns ns
TC=PeriodofthePCIClock *DefinebyTIMEOUTvalueinttheDEBICFGregister.ThetimeoutcounterbeginscountingwhenASorALEfails.If thetimeoutvalueisreachedbeforeanacknowledge(RDYgoinghigh,DTACKgoinglow)isobservedthenthe transferisterminatedandtheDEBI_TOflagisset.ThetimeoutvalueismeasuredintPCIclocks.
InIntelmodeacyclecanbeterminatedinthreeways.IfRDYishighwhenRDNorWRNfalls,the deviceisassumedtobereadyandthecyclewillcomplete.IfRDYislowwhenRDNorWRNfalls, thecycleterminateswhenRDYreturnshighorwhenthetimerexpires.IfRDYdoesnotreturn highafterthetimeout,theDEBIcontrollerwillnotstartanothertransactionuntilRDYishigh. InMotorolamodeacyclecanbeterminatedintwoways.ThefallingedgeofDTACKorwhenthe timerexpires.
**AnewtransactionwillnotbestarteduntilafterDTACKreturnshigh.
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11.I2CPort TheSAA7145isanI2Cbusmaster.TheI2CbusisusedtoconfigureotherPhiliscomponentsin thesystem.ItcanbeaccesseddirectlyorviaRPS. I2Cperformsserialbytetransfers.TheclockchosenisdivideddownfromthePCIsystemclockto arriveattheI2Cclockofaround100KHz. TworegistersareusedtogenerateI2Ctransfers.TheTransferControlRegister(IICTRF)contains theactualdatatobetransferredandthetransfertypeofeachbyte.Theactofplacingdatainthe IICTRFinitiatesthetransfer.TheStatusandClockRegister(IICSC)containsstatusandcontrol informationusedtodeterminethesourceofaninterruptandsetthespeedoftheI2Cclock. EachofthethreebytesintheIICTRFhastwoattributebitsassociatedwithit.Thesetwobitsare usedtodescribecontrolfunctionforthecorrespondingbyte.Eachbytecanbeconfiguredasa startbyte(11),continuebyte(10),endbyte(01)ornopbyte(00).Thestartbytedeterminesthe directionofthedatatransferwithbit0.Continuebytescanbesubaddressesordata.Astopbyte isthelastbyteinatransfer.Anopbyteisignored. Example: TotransferthebyteA5toaddress40subaddress21theIICTRFshouldbeprogrammedwith 4121A5E4.
IICTRF Bits 31:24 23:16 15:8 7:5 5:4 3:2 1 0 Name BYTE2 BYTE1 BYTE0 ATTR2 ATTR1 ATTR0 ERR BUSY Offset:70 Description Data/AddressByte2 Data/AddressByte1 Data/AddressByte0 AttributeInformationforBYTE2 AttributeInformationforBYTE1 AttributeInformationforBYTE0 GeneralErrorFlag TransferinProgress
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IICSC Bits 10:8 7 6 5 4 3 2 1 0 IICCC Value 7* 6 5 4 3* 2 1 0 ClockRate PCIClk/12 PCIClk/320 Name IICCC IICIRQ rsvd APERR DTERR rsvd rsvd ERR BUSY
Offset:74 Description I2CClockControl InterruptRequest Reserved AddressPhaseError DataTransmissionError Reserved Reserved GeneralErrorFlag TransferinProgress
PCIClk/6400 PCIClk/480 PCIClk/8 PCIClk/80 PCIClk/3200 PCIClk/120
*Donotusetheserates,dataforreferencepurposesonly.
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12.RegisterProgrammingSequencer(RPS) TheSAA7145usesRPStoprovideautomaticprogrammingoftheinternalregisters.RPS commandsareexecutedfromanexternalmemorylocationaccessedbyDMA.Thesecommands taketheformofaprogramthattheSAA7145'sRPSunitsequentiallyexecute. Topreventaccesstoregistersinactiveareasofthechip,aregisterbufferorShadowRAMis usedtostorevaluestobeloadedintotheinternalregistersata"safe"time.Thisfunction,called "upload",isperformedattheresolutionofthetimingcommandsWAITandCHECK.The shadowedregistersarelocatedinaddresses00hto2Ch.All12oftheshadowedregistersare updatedduringtheuploadregardlessofwhetherthevalueshavechangedornot.Duringthe upload,internalfunctionsaretemporarilyhaltedsocaremustbetakeninusingthesecommands. ThePAUSEcommandcanbeusedforawaitwhichdoesnotneedanupload. TheEventManager,DEBI,GPIOandI2Ccontrolsarenotshadowedsothesecommandsare executedimmediately,howevertheRPScommandstreamdoescontaincommandstoaidin properlytimingtheirexecution. TheUtilityRegisterisprovidedfortemporarystorageoranythingelse.Theregisterhasnoeffect onoperation. 12.1.RPSControl RPSactivityiscontrolledbytheRPSPregister.Theaddresspointerisprogrammedwiththe addressofthefirstcommandintheRPSlist.TheEnableRPS(ERPS)bitmustbesetwhile writingthestartaddressintheRPSPregister.ImmediatelyaftertheERPSbutissettheRPS DMAbeginstofetchcommandsfrommemorybeginningwiththecommandattheaddress pointer'slocation.FourDwordsarefetchedatatimeandloadedintoaninstructionqueue.The RPSunitexecuteseachcommandsequentiallytotheendofthequeueatwhichtimetheRPS DMAloadedthenextfourDwordsintheRPSlist.Aftereachcommandisexecutedtheaddress pointerisincremented.IfaWAIT,CHECKorPAUSEinstructionisencounteredinaRPSlist,the remainderofthequeueisconsideredinvalidandwillbereloadedaftertheconditionalhasbeen met. WhenanRPScommandisaccessingtheregisters,hostaccesstotheregistersismomentarily heldoff.The7145willexecutePCIretrycyclesuntiltheregistersetisavailableandthehostcycle willbecompletednormally.Nospecialactionisrequiredbysoftware.Thepossibilityofalockup conditionisnegatedby7145issuingtheTargetDisconnectRetrytothemasterattemptingto accessthe7145'sinternalregisters.Ifsuchaneventdoesoccur,theRPSunitofthe7145goes intoaspecialstateafterthecurrentcommandiscompleted,untilthehostretriesthedisconnected transaction. TheRPSpointeraddressesmustbeDwordaligned.IftheRPSPregisterisreaditwillindicatethe addressofcommandabouttobeexecuted.Bit0oftheRPSPreturnsthestatusoftheERPSbit. IfRPSisactive,anyattempttowritetotheaddresspointerwillshutdownRPSafterthecurrent instructionfinishesexecution. TheRPSPageAddressregistercanbeusedcontrolRPSwritestosystemmemory.Ifenabled, accessesoutsidetheRPSpagearenotallowedandaninterruptisgenerated.ThePageError Enable(ERPSP)bitislocatedatbit0oftheRPSpageregister,aoneenablespageerrors.Thisis
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bitisa0afterareset. RPShasasafetyvalveforcommandsthatcauseawaitincasetheeventdoesnotoccur.A waitingtimeoutvaluecanbeprogrammedinunitsofverticalsynchsorPCIclocksorboth.The featuremaybedisabledbyselectingnone.
TOSEL 00 01 10 11 TimeOutUsed None PCICounterTimeOut VSyncCounterTimeOut Both
12.2.CommandSet TheRPSCommandsetissimpledataflowmodel.Commandsareembeddedinthedatastream itself.TherearetencommandsavailableforuseintheSAA7145,theyare: * LDREG * STREG * STOP * JUMP * CHECK * WAIT * PAUSE * IRQ * CLR * SET CommandsarealwaysoneDWordandtheinstructioncodeisalwaysthetopbyteoftheDWord (1stnibble,bits31:28).Thesecondbyteisalwaysreservedandmustbewrittenwithzeroes.The bottomtwobytescontaincommandcontrolandthemeaningvariesfromcommandtocommand. OperandDWordsmayormaynotfollowthecommand. 12.2.1.LDREG LoadRegistercommandsplacedataintotheSAA7145'sinternalregisters.Thesecommands havethedataimmediatelyfollowingthecommandword.TheinstructioncodeforLDREGis5h. Thecommandwordhastwocontrolbytes,bits15:8indicatethenumberofdataDWordsthe follow.TheSAA7145doesnotallowformultipleDWordtransfershowever,sothisbyteshould alwaysbewrittenwitha1.Bits7:0indicatethedestinationstartingaddressofthedataword(s). ThestartingaddressistheDWORDaddressofthefirstregister. Ex.1Putthevalue21400280intoregister18h: 50000118 21400280
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12.2.2.STREG StoreRegistercommandsplacesthecontentsofinternalregistersintosystemmemory.The operandoftheStoreRegistercommandisanaddress.TheaddressmustbeinsidetheRPSpage oraninterruptisgeneratedandRPSstops.PageErrorscanbedisabledbysettingbit0inthe RPSpageregisterto1.TheinstructioncodeforSTREGis6h.Thecommandwordhastwo controlbytes,bits15:8indicatethenumberofdataDWordsthefollow.TheSAA7145doesnot allowformultipleDWordtransfershowever,sothisbyteshouldalwaysbewrittenwitha1.Bits 7:0indicatethesourcestartingaddressofthedataword(s).ThestartingaddressistheDWORD addressofthefirstregister. Ex.2Putthevalueofregister28hintomemoryaddresslocation034BC004: 60000128 034BC004 12.2.3.STOP TheStopinstructionhaltsexecutionofRPS.Ithasnooperands.Theinstructioncodeforthe STOPis3h.WhenthiscommandisexecutedtheERPSbitissettozeroandexecutionstops. Ex.3Thestopinstructionhasonlyonevariation: 30000000 12.2.4.JUMP TheJumpinstructionisusedtochangetheRPSAddressPointer.Theinstructioncodeforthe JUMPis4h.TheDWordfollowingtheJUMPindicatestheaddressatwhichtocontinue execution.TheJUMPcommandcanbemadetodependonastatusflag.Ifthespecifiedflagis setwhentheinstructionisexecutedtheJUMPistake,ifnotthenitisignored.AJUMPwithno statusflagsetistakenimmediately.Thelowertwobytesofthecommandspecifywhichflagsare usedtocontroltheJUMP.SeethesectiononFlagsfortheirdescription. Ex.4Startexecutionfromaddress00FC0800(unconditional) 40000000 00FC0800 12.2.5.IRQ AIRQinstructiongeneratesaninterruptonthePCIbus.Theinterruptismaskable.It'suseisup totheprogrammer.TheinstructioncodeforIRQis2h.TheIRQcommandcanbemadetodepend onastatusflag.IfthespecifiedflagissetwhentheinstructionisexecutedtheRPS_Ibitisset,if nottheIRQisignored.AIRQwithnostatusflagsetisdoneimmediately.Thelowertwobytesof thecommandspecifywhichflagsareusedtocontroltheIRQ.SeethesectiononFlagsfortheir description. Ex.5AnunconditionalIRQ: 20000000
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12.2.6.NOP ANOPcanbeexecutedinmanyways.Asetofclearflagwithunspecifiedcontrolisgood example. Ex.6TheNOPinstruction(byCLR): 00000000 12.2.7.WAIT TheWaitcommandisusedtotemporarilystopexecutionoftheRPSlistbasedonthestateof selectedstatusflags.TheWAITcommandwillstoptheRPSuntiltheselectedeventoccurs.When theeventoccurs,executioncontinuesimmediatelyaftertheregistershavebeenuploaded.Ifthe eventhasalreadyoccurredthenitislate,theRPSlatebitissetandRPSstops.Theinstruction codeforaWAITis9h.Thelowertwobytesofthecommandspecifywhichflagsareusedto controltheWAIT.SeethesectiononFlagsfortheirdescription. Ex.7Waitforbeginningofanevenfield: 90000004 12.2.8.CHECK TheCheckWaitcommandisusedtotemporarilystopexecutionoftheRPSlistbasedonthestate ofselectedstatusflags.TheCHECKcommandwillstoptheRPSuntiltheselectedeventoccurs. Iftheeventhasalreadyoccurredthenexecutioncontinuesimmediatelyaftertheregistershave beenuploaded.TheinstructioncodeforaCHECKis8h.Thelowertwobytesofthecommand specifywhichflagsareusedtocontroltheCHECK.SeethesectiononFlagsfortheirdescription. ACHECKcommandwithnoflagssetperformsanunconditionalupload. 12.2.9.PAUSE ThePausecommandisusedtotemporarilystopexecutionoftheRPSlistbasedonthestateof selectedstatusflags.TheCHECKcommandwillstoptheRPSuntiltheselectedeventoccurs.If theeventhasalreadyoccurredthenexecutioncontinuesimmediately.Registersarenotuploaded afterapausecommand.TheinstructioncodeforPAUSEisAh.Thelowertwobyteofthe commandspecifywhichflagsareusedtocontrolthePause.SeethesectiononFlagsfortheir description. 12.2.10.SET TheSetFlagscommandisusedtosetaparticularflag(orsetofflags).Itismostlikelythatiswill onlybeusedfordebuggingandoptimizingpurposes.TheinstructioncodeforSETis1h.The lowertwobytesofthecommandspecifywhichflagsaresetbytheSET.SeethesectiononFlags fortheirdescription. 12.2.11.CLR TheClearFlagcommandisusedtoclearaparticularflag(orsetofflags).ClearFlagisusedto setuptheflagsforawait.TheinstructioncodeforCLRis0h.Thelowertwobytesofthe commandspecifywhichflagsareclearedbytheCLR.SeethesectiononFlagsfortheir description.
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12.3.RPSFlags ThereareasetofflagsusedbyRPScommands.Theseare: DEBID: DEBIDone.SetwhenDEBIfinishesanaccess.ClearedbythestartofaDEBIaccess. IICD: I2CDone.SetwhentheI2Cbustransactionisfinished.ClearedwhenanI2Caccessis initiated. EVEN: Evenfield.HighduringanEvenField.LowduringandOddField. ODD: Oddfield.HighduringanOddField.LowduringanEvenField. HS: HCountSource.SetwhenthesourcelinecounterreachesthevalueoftheSLCT register.ClearedbyVerticalSync,orwhenthesourcelinecounterisreprogrammedto alinehigherthanthecurrentline.TheSourceLineCounterstopsafteritreachesit's maximumvalue,itdoesnotrollovertozeroandcontinuecounting. HT: HCountTarget.SetwhenthetargetlinecounterreachesthevalueoftheTLCT register.ClearedbytheStartofActiveVideo,orwhenthetargetlinecounteris reprogrammedtoalinehigherthanthecurrentline. EOL: EndofLine.SetwhenthelastpixelofalineisplacedintheFIFO,clearedbythestart ofthenextline. EAW: EndofActiveWindow.Setwhenthelastpixelofthecurrentactivewindow(asdefined bytheXandYwindowers)isputintotheFIFO.ClearedbyStartofthenextActive VideoWindow. GPIO3: GPIO3.SetwhentheGPIO3pingoeshigh.Clearedbytheresolutionofthewait. GPIO2: GPIO2.SetwhentheGPIO3pingoeshigh.Clearedbytheresolutionofthewait. GPIO1: GPIO1.SetwhentheGPIO3pingoeshigh.Clearedbytheresolutionofthewait. GPIO0: GPIO0.SetwhentheGPIO3pingoeshigh.Clearedbytheresolutionofthewait. VFE: VideoFIFOEmpty.SetwhentheFIFOgoesempty,clearedifanydataispresentint theFIFO. RPS_S: RPSSemaphore.SetbysoftwareintheIMR.Clearedonuse. ANY: ANY/ALL.Thisflagindicatedwhetheralloftheselectedflagsmustbeset(logical AND)foratrueconditionorifanyoftheselectedflags(logicalOR)indicateatrue condition.ThisflaghasnomeaninginSETorCLRcommands. INV: InvertFlag.Ifthisflagissetthentheconditionismetwhenleavingthestaterather thanenteringit.ThisflaghasnomeaninginSETorCLRcommands. TheBitpositionoftheflagsarethesameforallcommands.
Bit Flag Bit Flag 15 ANY 7 EAW 14 INV 6 EOL 13 RPS_S 5 HS 12 VFE 4 HT 11 GPIO3 3 ODD 10 GPIO2 2 EVEN 9 GPIO1 1 DEBID 8 GPIO0 0 IICD
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13.Clipper TheClipperintheSAA7145usesasoftwaregeneratedclipmasktoprovidevideowindow occlusioncapability.Thismethodprovidesanarbitrarynumberwindowclipsofanysizeorshare. AbitmaskisstoredinmemorybytheHostandisMasterreadviatheclipper'sownDMA. Theclipmaskdataisusedbitforpixeltodeterminewhetherornotapixeliswrittentothetarget. Theuserselectswhetherazerooraonedeterminesactivepixels.TheClipperdoesnotoperate intheYUV16outputmodebecauseoftheUVsubsampling. Inthecasethatthelineclipmaskisunabletobereadinthetimerequired,alltheremainingpixels ofthatlinewillbeclippedandoperationcontinueswiththenextline. SoftwareshouldtakecaretoonlychangethestateoftheClipperoutsideoftheActiveWindowto assureproperoperation. TheClipperhasitsownDMAcontrollerandiscontrolledbythefollowingregisters. ClipMaskDMABaseAddress(CDBA):ContainsthebaseaddressforDMAtransfers.Thisisthe addresscontainingthefirst32bitsofclippinginformation.LiketheVDBAonlythebottom24bits areincremented,sotheclipmaskislimitedtoa16megabytepage.
CDF Bits 28:24 21:26 9:0 Name CPO CPIX CLINE Offset:24 Description PixelOffsetintoDword NumberofDwordsperLineofClipMask NumberofLinesofClipMask
FirstPixelOffset(CPO):containstheoffsetintothefirstDwordofClipData.Thenumber programmedrepresentsthebitpositiontostartfromaftertheoptionalbyteswap.Thisoffsetis onlyusedonthefirstDwordofclipdatainaline. CPIX:containsthenumberofclipdatalongwordstofetchperline. CLINE:containsthenumberofclipdatalinesofclipdatatoread.
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CDMAC Bits 31 20:19 16 9:0 Name ECLIP CEND CPOL CPCH
Offset:28 Description EnableClipper EndiannessControls ClipperPolarity LinePitch
EnableClipping(ECLIP):enablestheClipperDMAtofetchdataandpresentclipdatatothePixel Formatter. ClipDataPolarity(CPOL):thepolarityofthisbitisthepolarityusedforclippingpixels. ClipDataPitch(CPCH):thisisthedifferenceinaddress(insystemmemory)fromthefirstclip dataDwordofonelinetothefirstclipdataDwordofthenextline. Endianness(CEND):controlsanoptionbyteswapandwhichendoftheDwordtostartfrom.This firstandsecondbitsshowbelowareastheyappearonthePCIbus(CEND[0]=0).
CEND[0] 0 1 CEND[1] 0 1 Swapping Noswap 4byteswap Startfrom BigEnd LittleEnd 1st,2ndbit 31,30 7,6 1st,2ndbit 31,30 0,1
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14.PCIInterface ThePCIinterfaceoftheSAA7145iscompliantwiththePCILocalBusSpecificationRevision2.1 andisbothamasterandaslave.ThePCIconfigurationspaceuseisgivenbelowinthetable. InternalregistersoftheSAA7145areaddressedbyusingthebaseaddressregisterandadding theregisteroffset.ThisregisteroffsetisalsousedinRPSprogramming.
OFFSET 00h 04h NAME DeviceID VendorID StatusRegister BIT 31:16 15:0 31 30 29 28 27 26:25 24 23 22 21 9 8 7 6 5 4 3 2 1 0 31:8 7:0 15:8 31:7 6:0 31:24 23:16 15:8 7:0 TYPE/VALUE RO/7145h RO/1131h RO RO/0b RO RO RO/0b RO/01b RO RO/1b RO/0b RO/0b RW/0b RW/0b RO/0b RW/0b RO/0b RO/0b RO/0b RW/0b RW/0b RO/0b RO/048000h RO/00h RW/00h RW/D00000h RO/00h RO/18h RO/09h RO/01h RW/00h DESCRIPTION SAA7145 PhilipsSemiconductors DetectedParityError SignaledSystemError ReceivedMasterAbort ReceivedTargetAbort SignaledTargetAbort DEVSELTiming=Medium DataParityErrorDetected FastBacktoBackCapable=Yes UDFSupported=No 66MHzCapable=No FastBacktoBackEnable SERR#Enable WaitCycleControl ParityErrorResponse VGAPaletteSnoop MemoryWriteandInvalidateEnable SpecialCycles BusMasterEnable MemorySpaceEnable IOSpaceEnable OtherMultimediaDevice Thisvalueloadedduringconfiguration Thisvalueloadedduringconfiguration 6sec 2.25sec SelectsINTA# Thisvalueloadedduringconfiguration
CommandReg.
D8h 0Ch 10h 3Ch
ClassCode RevisionID LatencyTimer BaseAddress Max_Lat Min_Gnt InterruptPin InterruptLine
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14.1.ThePCIMaster ThePCIMasterblockisresponsibleforensuringthatallDMAswithintheSAA7145areserviced. ItcontainsamodifiedroundrobinmechanismtoassuretheFIFOoverflowsandunderflowsdonot occur.Theorderofhierarchyisasfollows: 1. RPS 2. Audio 3. DEBI 4. Clipper 5. Video ThelistisrepeateduntilnoDMAsarependingoruntilthelatencytimerrunsout.Itisimportantto notethatpriorityflowisalwaysdownwards.Thebusownerignoresrequestsfromaboveifthereis arequestfrombelow. Example:ifDEBIisthecurrentownerandbothRPSandVideohavependingDMAs,thenext ownerwillbetheVideoDMA.HoweverifVideohadnotrequestedservicethenRPSwouldbethe nextowner. AnotherwaytolookatthisisthateachofthefiveDMAsseesadifferentprioritylist.Asbelow:
Owner: highest next next last RPS Audio DEBI Clip Video Audio DEBI Clip Video RPS DEBI Clip Video RPS Audio Clip Video RPS Audio DEBI Video RPS Audio DEBI Clip
IfAudioownsthebus,thenDEBIhasthehighestprioritytobethenextowner.IfDEBIhasno requestthenitfallstotheClipper,andsoon. IntheeventofaretrycyclefromthePCItarget,arbitrationwillbelockeduntiltheretryisresolved.
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15.TheEventManager TheSAA7145'seventmanagercontainsanintegralinterruptandstatusmonitoringsystem.Itis capableofaccumulatingdataforusebysoftwaretomonitorsystemperformanceandprovide systemcontrol. 15.1.InterruptControl TheSAA7145supportsinterruptsfrommanydifferentsources.Thesesourcesareavailableas monitorbitsintheInterruptMonitorRegister(IMR).EachinterruptcanbemaskedintheInterrupt EnableRegister(IER).Ifaninterruptisenabledanditsmonitorbitgoesactivethecorresponding bitisset(1)intheInterruptStatusRegister(ISR).IfanybitoftheISRisactive(1)thePCIINTA# pinissettolow. TheIMRandISRarespecialregistersinthatwritingtothemhasspecialeffects.Writingaoneto anIMRbitgeneratesaninterruptifthecorrespondingenableisset.WritingazerotoanIMRbit hasnoeffectonthatbit.WritingaonetoanISRbitclearsthecorrespondinginterrupt.Writinga zerotothisregisterhasnoeffectonthestatusbit. Somesourcesareprovidednotwiththeintentionthattheywillgenerateinterruptsbutcanbe routedtoeventcountersorGPIOpins.Reservedbitsalwaysreadbackasinactive(zero). Interruptsourcesaredescribedbelow: PCIParityErroronRead.ThisbitissetwhenaPCIparityerrorisdetectedduringa readofPCIdata. PPEW: PCIParityErroronWrite.ThisbitissetwhenaPCIparityerrorisreportedbyathe targetofaPCIwrite. PABO: PCIAccessAbort.ThisbitissetwhenaPCItransferisterminatedwitheitheratarget -ormaster-abort. DEBI_I: DEBIinterrupt.ThisbitissetwhentheDEBIport'sXIRQpingoesactive. DEBI_TO: DEBITimeOutError.ThisbitissetwhenaDEBItransfertimesout. DEBI_D: DEBIDone.ThisbitissetwhenaDEBItransfercompletes. IIC_E: I2CError.ThisbitissetwhentheI2Cportfinishesacommand. ARI: AudioRangeInterrupt.ThisbitissetbytheAudioDMAcontrollerdependentonthe programmingoftheARNGregister. UPLD: RPSUpload.ThisbitissetduringthetimeanRPSuploadistakingplace.Settingthe uploadbitwillforceanuploadtooccurifRPSisnotrunning. RPS_PE: RPSPageerror.ThisbitissetwhenRPStriestowritetoanaddressoutsidetheRPS pagecurrentlyintheRPSpageregister. RPS_L: RPSLateError.ThisbitissetifRPSisunabletocompleteexecutionbythetimethe originalstartconditionoccursagain. RPS_TO: RPSTimeOut.ThisbitissetifRPSisinawaitstateforadurationexceedingthetime outvalue. RPS_S: RPSSemaphore.Thisbitissetbysoftwareforuseinsynchronizingthevideostream. ItisclearedbyRPS. RPS_I: RPSInterrupt.ThisbitissetbytheRPScommandINTERRUPT.
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DataSheet SAA7145
VideoDMAAddressProtectionError.ThisbitissetiftheVideoDMAcontroller attemptstoaccessanaddressbeyondtheFIFOprotectionaddress. VFE: VideoFIFOEmpty.ThisbitissetifthevideoFIFOisempty. VFO: VideoFIFOOverflow.ThisbitissetifanoverflowoccursintheVideoFIFO. AFO: AudioFIFOOverflow.ThisbitissetifanoverflowoccursintheAudioFIFO. CFU: ClipperFIFOUnderflow.ThisbitissetwhentheClipmaskisn'tloadedintimeforuse bytheclipper. FID: FieldID.ThisbitechoesthefieldIDofthefieldthatiscurrentlybeingprocessed. FIDN: FieldIDNot.ThisbitechoestheinvertofthefieldIDofthefieldthatiscurrentlybeing processed. VBI: VerticalBlankInterval.Thisbitissetwhenthevideosourceentersverticalblanking. HBI: HorizontalBlankInterval.Thisbitissetwhenthevideosourceentershorizontal blanking. GP0: GPIO0Status.ThisbitreflectsthestatusoftheGPIO0pin. GP1: GPIO1Status.ThisbitreflectsthestatusoftheGPIO1pin. GP2: GPIO2Status.ThisbitreflectsthestatusoftheGPIO2pin. GP3: GPIO3Status.ThisbitreflectsthestatusoftheGPIO3pin. EC1: EventCounter1.Thisbitissetwheneventcounter1reachesitsthreshold. EC2: EventCounter2.Thisbitissetwheneventcounter2reachesitsthreshold. MASTER: Masterinterrupt.IntheISRthisbitreflectsthesumoftheenabledinterruptflags,it clearedautomaticallywhennointerruptispresent.IntheIERthisbitisusedasthe Masterinterruptenableforallflags.Thisbitmustbesetforanyofthemonitorbitsto causeaninterruptonINTA#.IntheIMRthisbitalwaysreadsbackaszero.
ISR IER IMR bit name bit name bit name bit name 31 PPER 23 ARI 15 VBI 7 GP3 Offset:48/configure Offset:4C Offset:50 30 PABO 22 UPLD 14 HBI 6 GP2 29 PPEW 21 RPS_S 13 FIDN 5 GP1 28 DEBI_D 20 RPS_I 12 FID 4 GP0 27 DEBI_I 19 RPS_TO 11 AFO 3 rsvd 26 DEBI_TO 18 RPS_L 10 CFU 2 EC2 25 IIC_E 17 RPS_PE 9 VPE 1 EC1 24 IIC_D 16 VFE 8 VFO 0 MASTER
VPE:
15.2.EventMonitors TheSAA7145hasthecapabilitytoprovidestatisticaldataonanyoftheinterruptsourceswhether theyareenabledornot.TheECCisusedtoselectthesourceofthecountersansalsotoclear andenablethem.TheEventCounterSelectsbits(ECSEL)areusedtoselectwhichsourcegoes tothecounter.ECSELisloadedwiththebitpositionoftheinterrupttocount.
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DataSheet SAA7145
AmonitorbitcanbefedintooneoftwocountersinttheEventCounterRegister(ECR).TheECR containstwo10bitcounters.ControloftheECRisdoneintheEventCounterControlregister (ECC).TheEventCounterThresholdRegister(ECT)setsathresholdvalueforeachcounter'sthe monitorbit.Whenthisthresholdisreachedthecorrespondingmonitorbitisset,thecounterresets andcontinuescounting. TheENxbitsenableeachcountertobegincounting.WritingaoneinanENxbitenablesthat counter.Azerostopsthecounterbutdoesnotclearit. TheCLRxbitsallowthecounterstobeclearedindependentlyofeachother.Writingaonetoone ofthebitclearsthecountertozero,writingazerohasnoeffect.TheCLRxbitisawriteonlynon persistentbit,readswillalwaysreturnazero. ForGPIOcounting,theedgebeingcountedcanbecontrolledviatheGPIOregister. Note:EventFIDNisnotavailableforcounting.
ECC Bits 15:11 10 9 8 7:3 2 1 0 ECR Bits 31:20 19:10 9:0 ECT Bits 31:20 19:10 9:0 Name rsvd ECT2 ECT1 Name rsvd ECR2 ECR1 Name ECSEL2 rsvd EN2 CLR2 ECSEL1 rsvd EN1 CLR1 Offset:5C Description Interruptbitpositionforcounter2 Reserved Enablecounter2 Clearcounter2 Interruptbitpositionforcounter1 Reserved Enablecounter1 Clearcounter1 Offset:54 Description Reserved EventCounterRegister2 EventCounterRegister1 Offset:58 Description Reserved EventCounterThreshold2 EventCounterThreshold1
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16.GeneralPurposeI/OPort(GPIO) TheGPIOportisassetoffourgeneralpurpose/statusI/Opins.Thesepinscanbeusedto monitoranyoftheinternalstatusbitsintheIMRortocommunicatestatustoorfromanother deviceontheboard.Thepinspowerupasinputsandhavesoftinternalpullupresistors.They areeachprogrammedbyasetofbitslocatedintheGPIOControlRegister. TheminimumpulsewidthofasignalonaGPIOpinmustbeatleasttwoPCIclockstoensurethat thesignalwillbecaptured. DIR: thisbitisusedtocontrolthedirectionoftheGPIOpin.Azeroindicatedthepinisaninput. IOS: thisbitreportsthestatusofthepinininputmodeandiswrittentoinoutputmode. MIO: thisbitisusedtosetupthebitasaninterruptmonitorbitoraIOpin.Azerosetsthepinto IOmode,aonewillputthepininmonitormode.Ifapinisdefinedasaninputandisin monitormode,thedataonthepinisignored. MSEL: Inmonitormode,the5bitregisterisusedtoselectwhichoneoftheInterruptsappearson theoutputpin.Thenumberprogrammedrepresentsthebitpositionoftheinterruptto appearonthepin. InIOmode,theMSEL[1:0]bitsareusedtodeterminethetransitionedgeusedtocausean eventofinterrupt: 00:levelonly(norecommendedforinterruptuse) 01:risingedge 10:fallingedge 11:bothedges
GPIOC bits name bits name bits name bits name 31:27 MSEL3 23:19 MSEL2 15:11 MSEL1 7:3 MSEL0 Offset:50 26 MIO3 18 MIO2 10 MIO1 2 MIO0 25 DIR3 17 DIR2 9 DIR1 1 DIR0 24 IOS3 16 IOS2 8 IOS1 0 IOS0
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17.PinList Thetablebelowdescribesthepinsandtheirfunctions.
Group AUD AUD AUD DEBI DEBI DEBI DEBI DEBI GPIO IIC IIC PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PWR PWR VP VP VP VP VP PinName ACLK ADAT AWS AS_ALE DTACK_RDY LDS_RDN RWN_SBHE XIRQ GPIO[3:0] SCL SDA AD[31:0] C/BE#[3:0] CLK DEVSEL# FRAME# GNT# IDSEL INTA# IRDY# PERR# REQ# RST# STOP# TRDY# VDD VSS FID HS LLC PXQ VPI[15:8] Type Ip Ip Ip O Ip O O I I/Oph O I/Opo I/O I/O I I/O I/O I I O I/O I/O O I I/O I/O I/Oo I/Oo Ip Ip Ip Description AudioI2SBitClock AudioI2SDataInput AudioI2SWordSelect DEBIPortAddressStrobeorAddressLatchEnable DEBIPortDataTransferAcknowledgeorReady DEBIPortDataTransferControlSignal DEBIPortDataTransferControlSignal DEBIPortInterruptRequest GeneralPurposeInput/OutputPins I2CSerialClock.Clockrateisdeterminedbythevalueprogrammedintthe IICCTLregister I2CSerialData PCIMultiplexedaddressanddatabus PCIMultiplexedCommandandByteEnables PCIClock PCIDEVSEL#signal PCITransferControl PCIBusArbitrationSignal PCITransferControl PCIInterruptLine PCITransferControl PCIParityErrorSignal PCIBusArbitrationSignal PCIBusGlobalReset PCITransferControl PCITransferControl Powerpins.5V Groundpins.0V FieldIdentificationInput HorizontalSync LineLockedClick.Thevideodataclock PixelQualifier.ValiddataisdefinedbythispinhighandarisingedgeonLLC. Uppereightbitsofthevideoportdata.Alsothese8bitsareusedtoreceivethe D1stream Lowereightbitsofthevideoportsdata.ThesebitsareignoredinD1mode. VerticalSync
VP VPI[7:0] Ip VP VS I/Op I=InputPin O=OutputPin I/O=BidirectionPin p=weakInternalpullup h=highdriveoutput(12mA),standarddriversare6mA o=OpenCollectoroutput
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18.PinOut
Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name VDD VDD VPI[11] VPI[12] VPI[13] VPI[14] VPI[15] VDD VSS VS HS LLC PXQ VDD VSS FID AWS ACLK ADAT VDD VSS INTA# RST# VSS CLK VDD VSS GNT# REQ# AD[31] AD[30] VDD VSS AD[29] AD[28] AD[27] AD[26] AD[25] VDD VDD Group PWR PWD VP VP VP VP VP PWR PWR VP VP VP VP PWR PWR VP AUD AUD AUD PWR PWR PCI PCI PWR PCI PWR PWR PCI PCI PCI PCI PWR PWR PCI PCI PCI PCI PCI PWR PWR Pin# Name Group 41 VSS PWR 42 VSS PWR 43 AD[24] PCI 44 C/BE#[3] PCI 45 IDSEL PCI 46 AD[23] PCI 47 VDD PWR 48 VSS PWR 49 AD[22] PCI 50 AD[21] PCI 51 AD[20] PCI 52 AD[19] PCI 53 VDD PWR 54 VSS PWR 55 AD[18] PCI 56 AD[17] PCI 57 AD[16] PCI 58 C/BE#[2] PCI 59 FRAME# PCI 60 VDD PWR 61 VSS PWR 62 IRDY# PCI 63 TRDY# PCI 64 DEVSEL# PCI 65 STOP# PCI 66 PERR# PCI 67 VDD PWR 68 VSS PWR 69 rsvd PCI 70 PAR PCI 71 C/BE#[1] PCI 72 73 74 75 76 77 78 79 80 AD[15] VDD VSS AD[14] AD[13] AD[12] AD[11] VSS VSS PCI PWR PWR PCI PCI PCI PCI PWR PWR Pin# 81 82 83 84 85 86 87 88 89 90 91 91 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Name Group VDD PWR VDD PWR AD[10] PCI AD[9] PCI AD[8] PCI C/BE#[0] PCI AD[7] PCI VDD PWR VSS PWR AD[6] PCI AD[5] PCI AD[4] PCI AD[3] PCI VDD PWR VSS PWR AD[2] PCI AD[1] PCI AD[0] PCI XAD[15] DEBI VDD PWR VSS PWR XAD[14] DEBI XAD[13] DEBI XAD[12] DEBI XAD[11] DEBI VDD PWR VSS PWR XAD[10] DEBI XAD[9] DEBI XAD[8] DEBI RWN_SH DEBI Be VDD PWR VSS PWR AS_ALE DEBI LDS_RD DEBI N UDS_WR DEBI N DTACK_ DEBI RDY XIRQ DEBI VDD PWR VDD PWR Pin# 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Name VSS VSS XAD[0] XAD[1] XAD[2] XAD[3] VDD VSS XAD[4] XAD[5] XAD[6] XAD[7] VDD VSS SCL SDA rsvd GPIO[3] GPIO[2] VDD VSS GPIO[1] GPIO[0] VPI[0] VPI[1] VPI[2] VDD VSS VPI[3] VPI[4] VPI[5] VPI[6] VDD VSS VPI[7] VPI[8] VPI[9] VPI[10] VSS VSS Group PWR PWR DEBI DEBI DEBI DEBI PWR PWR DEBI DEBI DEBI DEBI PWR PWR IIC IIC GPIO GPIO PWR PWR GPIO GPIO VP VP VP PWR PWR VP VP VP VP PWR PWR VP VP VP VP PWR PWR
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DataSheet SAA7145
A.AppendixA:RPSProgrammer'sReference A.1.ProgrammingExamples RPShasmanypossibleuses,belowarecoupleofthemorelikely. Ingeneral,anRPSlistiscomposedoftwosectionsalthoughthisisnotrequires.Thefirstsection isusedforgeneralconfigurationandsetup.Thefirstsectionisoptionalbecausetheinternal startupprogrammingcanalsobeaccomplishedbythhost.Thesecondsectionisthetime dependentpart.Thissectioniswheretheregistersarereprogrammedforthedifferenttasks. ItisnotrecommendedthattheregistersbeaccessedbythehostwhileRPSisrunning,these accessesarepermittedhoweverandwillnotcausethechiptohangbutmayhaveunpredictable results.Thereisoneexceptiontothisrule:ifaregisterisnotusedintheRPSlist,itwouldbesafe toreprogramitfromthehostduringRPSexecution. A.2.RPSBasics ThisRPScodesegmentshouldbeusedtocleanlyswitchvideoonafteramovetoanewlocation orachangeinsize,formatorscalingfactor.Itisintendedtobeusedinapplicationswhere multipledestinationsandspecialvideotasksarenotrequires. Ref: Hex Code Op Code where: 50000100 LDREG FB000000 50000104 LDREG FB080000 scale: 5000001C LDREG 00000003 50000118 LDREG 94000400 winsiz: 50000110 LDREG 00880280 50000114 LDREG 000D00F0 format: 50000108 LDREG 8CA01000 00000080 CLEAR upload: 80000080 CHECK stop: 30000000 STOP Operand 01,00 FB000000 01,04 FB080000 01,0C 00000003 01,18 94000400 01,10 00880280 01,14 000D00F0 01,08 8CA01000 EAW EAW Comment Load reg 0 00.Vid DMA Base Load reg 4 04.Vid DMA Prot Load reg 0C 0C.Port Control Load reg 18 18.Scaling mode Load reg 10 10.H Source Ctl Load reg 14 14.V Source Ctl Load reg 8 08.Vid DMA Ctl Clear the EAW Flag Wait for EAW Stop RPS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Theabovecodeassumesvideoisalreadyrunningandshouldbeusedto(re)startthevideo DMA.Tousethisprogramtoinitializethechipmodifythelistasshownbelow. 13 upload: 80000000 14 stop: 30000000 CHECK STOP Upload Stop
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DataSheet SAA7145
A.3.UsingRPStosendvideototwolocations RPScanbeusedtodivideanincomingvideostreamintotwofieldbasedstreamswithseparate destinations.ThefollowingprogramsetstheSAA7145tosendtwoNTSCfieldstodifferent locations.TheofffieldsaresenttotheframebufferinRGB32scaledto200x150.Theevenfields aresenttosystemmemoryinYUV16at320x240.Thelistassumesabaseaddressof00400000. Ref: Hex Code Op Code setup: 5000030C LDREG 00000F03 DW 50000110 LDREG 00800280 DW 50000114 LDREG 001400F0 DW 80000000 CHECK odd: 50000100 LDREG A0200000 DW 50000108 LDREG F8801000 DW 50000118 LDREG 21400280 DW 00000008 CLEAR 80000008 CHECK even: 50000100 LDREG 00600000 DW 50000108 LDREG F8840140 DW 50000118 LDREG 22000400 DW 00000004 CHECK 80000004 CHECK 40000000 JUMP 0040001C DW Operand 01,0C 00000F03 01,10 00800280 01,14 001400F0 01,00 A0200000 01,08 F8801000 01,18 21400280 ODD ODD 01,00 00600000 01,08 F8840140 01,18 22000140 EVEN EVEN odd Comment Load reg C 0C.Vid Port Ctl Load reg 10 10.H Source Ctl Load reg 14 14.V Source Ctl Force Upload Load reg 0 00.Vid DMA Load reg 8 08.Vid Ctl Load reg 18 18.Scaling Mode Clear the odd flag Wait for odd field Load reg 0 00.Vid DMA Load reg 8 08.Vid Ctl Load reg 18 18.Scaling Mode Clear the even flag Wait for even field Jump always to odd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Explanation: ThisRPSprogramisdividedintothreesections.Setupinitializestheregisters.SectionOdd preparestheSAA7145fromtransferoftheoddfieldtotheframebuffer.SectionEvenprepareit fortransferoftheevenfieldtosystemmemory. Lines16:loadthreeregistersbeginningwithregister0C.Thesethreeregisterssetupthe WindowGeneratorandtheVideoport.Sincethesethingsdonotchangebetweenfieldstheyare placedoutsidethemainloop.NotethatalthoughthreeLOADcommandsareperformedherethe valuesareonlywrittentotheShadowRAM,nottheworkingregisters.Ifanyregistersinthe shadowRAMhadbeenpreviouslyused(byanotherapplication,etc.)theywillstillcontainthat informationsoitisalwaysagoodideatocompletelyreloadtheshadowRAMbeforerunninga newRPSlist. Line7:thislinecontainstheunconditionalCHECK.Thisinstructionmovesthedataintheshadow
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DataSheet SAA7145
RAMintotheactualworkingregisters.Alternatively,theentiresetuppartoftheRPSlistcouldbe omittedandinsteadtheinitialconfigurationcouldbewrittentotheShadowRAMfollowedbyan uploadgeneratedviatheIMRUploadBit. Lines811:thisisthebeginningofthemainloop.TheoddsegmentloadstheDMAbaseaddress andconfigurestheDMAfortheoddfield.TheseregisterssetuptheDMAtotheframebufferand configurethepixelformatterforRGBdata.Bit31oftheVideoDMAControlRegister(VDMAC)is settostartthevideoDMA.Itisimportanttonotethatthisdoesnothappenuntiltheregistersare uploadedintotheworkingregisterfromtheShadowRAM. Lines1213:loadregister18.Thiscommandloadsthescalercontrol.Itisconfiguredfor200x150 withanFMODEof2. Lines1415:line14containstheCLEARODDwhichclearstheflag.Thisisneededtoensure thatvideocapturedoesnotbegininthemiddleofafield.Line15containstheconditionalCHECK ODDwhichwaitsuntiltheoddfield.WhentheoddfieldflagissettheShadowRAMisuploaded intotheworkingregisters.ThisenablestheSAA7145tobeginit'svideoDMAwhentheActive VideoWindowisreached.ExecutionoftheRPSlistcontinuesimmediatelyaftertheupload. Lines1621:thesecommandsloadtheshadowRAMwiththeoperationvaluesfortheeventfield. Thisis320x240YUVdatawithanFMODEof2. Lines2223:thissegmentcontainstheCLEAREVENandtheconditionalCHECKEVEN.These linesareusedtouploadtheshadowRAMintotheworkingregistersatthebeginningoftheeven field.ExecutionoftheRPSlistcontinuesimmediatelyaftertheupload. Lines2425:theJUMPcommandistheloopingpointofthelist.TheRPSpointerismovedtothe addressthatfollowsthiscommand,inthiscasetheaddressoftheoddfieldconfiguration.
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DataSheet SAA7145
B.AppendixB:InterfacingtoStandardPhilipsParts B.1.ProgrammingHints ThemostlikelycandidatesforconnectiontotheVideoinputportaretheSAA7110andSAA7111. Thefollowingtablesindicatewhattoputintheregistersforvariousinputs. SAA7145toSAA7111Programming
YUV16 SAA7111 Subaddr 2 3 4 5 6 8 9 A B C D E 10 11 12 SAA7145 VPZ XSS SF FD[] XWS XWZ YWS YWZ *AssumesMode0 *AssumesMode6 1 1 1 3 88 2D0 0C F0 AE 300 11 11F 0D 12 0 0 0 0 1 0 0 0 0 1 NTSC CVBS* D8 23 0 0 F0 A8 12 80 47 40 0 1 48 0C 80 C8 C8 2 12 2 YUV16 PAL ? D1 NTSC ? D1 PAL ? ? ? Svideo** DD
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SAA7145toSAA7110Programming
SAA7145 VPZ XSS SF FD[] XWS XWZ YWS YWZ NTSC 1 1 0 0 88 280 0C F0 PAL 1 1 0 0 AE 300 11 11F
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DataSheet SAA7145
C.AppendixC:PackageOutline
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